Industrial Focus
Curriculum designed by experts to mimic real-world “Bug Hunting” environments.
Coverage-Driven
We teach how to prove a design is 100% verified, not just that it “works.”
Portfolio-Ready
All project code is documented professionally, ready for your GitHub portfolio.
Comprehensive Syllabus
7 Modules tailored to take you from architectural concepts to synthesizable hardware.
Capstone Projects
I2C Controller Design & SV Verification
Multi-master/Slave logic with Start/Stop detection.
SV Layered Testbench with dynamic arrays for packet handling.
AXI4-Lite Slave IP (UVM-based)
Synthesizable AXI4-Lite interface with register banks.
UVM environment with specialized sequences for read/write stress testing. SVA (Assertions) for protocol compliance.
RISC-V Based SOC Project
Integrating a RISC-V core with UART, RAM, and a Timer over an APB Bus.
Writing simple C-code to run on the hardware for HW/SW co-verification.
High-Speed Async FIFO & CDC
Dual-clock architecture with Gray-coded pointers for Clock Domain Crossing.
Assertion-based verification (SVA) for full/empty flags and data integrity checks.
SPI Protocol Interface (Master/Slave)
Configurable CPOL/CPHA modes with interrupt generation logic.
UVM Agent development with reactive sequencer for protocol stress testing.
DMA Controller with Scatter-Gather
Direct Memory Access engine supporting burst transfers and linked-list descriptors.
System-level verification ensuring data coherency and bus arbitration logic.
Advanced VLSI Physical Design: RTL-to-GDSII Modules 📟
Foundations of Digital Electronics & ASIC/FPGA
Core Concepts: Logic Gates, Combinational/Sequential Circuits (Mux, Flip-flops), ASIC vs. FPGA architecture.
Design Flow: Overview of the RTL-to-GDSII trajectory and design abstractions.
Example:
Analyzing why a D-Flip-Flop is preferred over a Latch in synchronous PD to avoid timing glitches.
Verilog HDL for Physical Design Perspective
Synthesis-Friendly Coding: Writing RTL that translates efficiently to hardware.
Netlist Prep: Understanding how Verilog constructs turn into logic gates.
5 HDL Projects: Coding blocks like a FIFO Buffer or an ALU specifically for synthesis.
ASIC & FPGA Design Flow Overview
Architectural Differences: Frontend (Logic) to Backend (Physical) transitions.
Methodology: Hierarchical (Divide & Conquer) vs. Flat design styles.
Example:
Implementing a hierarchical flow for a Multi-core Processor to manage complexity vs. a Flat flow for a small UART controller.
Linux & Scripting for VLSI
OS Mastery: Linux/Unix file permissions, grep, sed, and awk.
Automation: Tool automation using TCL (standard for EDA), Perl, and Python.
Example:
Writing a TCL script to automatically generate timing reports for 50 different corners in a single run.
Logical Synthesis & Netlist Preparation
Translation: Converting RTL to Gate-level Netlist using Synopsys Design Compiler or Cadence Genus.
Constraints: Creating the SDC (Synopsys Design Constraints) file (clocks, input/output delays).
Example:
Setting a set_max_fanout constraint to ensure a signal doesn’t drive too many gates, preventing signal degradation.
Floorplanning & Power Planning
Macro Placement: Strategic positioning of IPs and Memory blocks.
Power Grid (PNS): Designing Rings, Straps, and Rails.
Example:
Calculating the “Core Utilization” to ensure there is enough room for routing while keeping the chip size small (e.g., aiming for 70% utilization).
Placement & Routing
Placement: Standard cell positioning and congestion analysis.
Routing: Global and Detailed routing, Metal layer constraints, and Crosstalk.
Example:
Using “Shielding” (placing VSS wires next to a sensitive clock line) to prevent electromagnetic interference (crosstalk).
Clock Tree Synthesis (CTS)
Clock Distribution: Balancing Skew (difference in arrival time) and Latency (insertion delay).
Optimization: Using H-Trees and Clock Gating for power efficiency.
Example:
Implementing an H-Tree structure to ensure the clock signal reaches the top-left and bottom-right corners of the chip at exactly the same time.
Static Timing Analysis (STA)
Calculations: Setup/Hold time checks and Slack calculation.
MMMC: Multi-Mode Multi-Corner analysis (checking performance at -40°C vs 125°C).
Example:
Fixing a Hold violation by adding “Delay Buffers” to a short path to ensure data doesn’t arrive too early.
Low Power Design Concepts
Techniques: Multi-VDD, Power Shut-Off (PSO), and Clock Gating.
Verification: Implementing UPF (Unified Power Format) to define power intent.
Example:
Adding “Level Shifters” when a signal travels from a 0.8V domain to a 1.2V domain to prevent logic failure.
Parasitics and Extraction
RC Extraction: Extracting resistance and capacitance from interconnects using StarRC.
Back-annotation: Feeding delay data back into STA for final signoff.
Example:
Analyzing how “Coupling Capacitance” between two parallel metal wires slows down signal transitions.
Physical Verification & Signoff
Checks: DRC (Design Rule Check), LVS (Layout vs Schematic), and Antenna checks.
Tools: Using industry-standard Siemens Calibre or Cadence ICV.
Example:
Fixing a “Minimum Spacing” DRC error by manually moving two metal traces that are too close for the foundry to manufacture.
Standard Cell Libraries & ASIC Flow Setup
Files: Understanding .lib (timing), .lef (physical), and .def (design) files.
Characterization: How cells like Inverters are modeled for power and timing.
Physical Design Projects (The “Portfolio” Phase)
5 Industry-Standard Projects: Complete Netlist-to-GDSII implementation.
Featured Project: UART/SPI Controller Implementation
- 1 Synthesize Netlist.
- 2 Floorplan with 75% utilization.
- 3 Build Clock Tree.
- 4 Verify GDSII via DRC/LVS.
Aptitude, Puzzles & Interview Prep
Logic: Quant, Logical Reasoning, and VLSI Brain Teasers.
Assessments: Weekly quizzes and timing-diagram-based puzzles.
Career Support & Job Preparation
Resources: 5000+ Interview Q&A database.
Global Reach: Specialized Resume building for Indian, US, and EU markets.
Placement: Guaranteed assistance and expert mock interviews.
Expert Mentorship & Support
Access: 24×7 support and live doubt clearing.
Networking: Exclusive sessions with Senior PD Engineers from companies like Intel, NVIDIA, or TSMC.