Digital Systems Architecture
Interactive engineering guide to digital logic, circuit design, and silicon-level architecture.
01. Digital Basics
Codes & Systems
Understanding BCD (8421), Excess-3, and Gray Code. Gray code is critical in rotary encoders as only one bit changes at a time.
Decimal 2: 0011 (Gray)
Decimal 3: 0010 (Gray) ← Only 1 bit diff
Arithmetic Overflow
In n-bit signed arithmetic, overflow occurs if the carry into the sign bit ≠ carry out of the sign bit.
02. Boolean Algebra
Fundamental Logic Laws
- Commutative: A + B = B + A
- Associative: (A+B)+C = A+(B+C)
- DeMorgan: ¬(A ∧ B) = ¬A ∨ ¬B
- Distributive: A(B+C) = AB + AC
- Consensus: AB + BC + AC’ = AB + AC’
F = A’BC + ABC + ABC’
F = BC(A’ + A) + ABC’
F = BC + ABC’
// K-Map 4-Variable Adjacency
Cell 0 is adjacent to 1, 2, 4, 8.
03. Standard Symbols & Logic
AND Gate
Product: Y = A·B
OR Gate
Sum: Y = A+B
NOT Gate
Inverter: Y = A’
CMOS Realization (NOT Gate)
PMOS (Top): Conducts when input is LOW (0V), pulling output to VDD (High).
NMOS (Bottom): Conducts when input is HIGH (5V), pulling output to GND (Low).
This complementary structure ensures zero static power consumption.
Universal Logic
NAND and NOR are universal because any logic function can be implemented using only these gates. For example, a NOT gate is a NAND with both inputs tied together.
04. Complex Circuit Diagrams
Half Adder Logic Diagram
Implementation using XOR and AND gates.
Full Adder Block Diagram
Constructed using two Half Adders and an OR gate.
05. Combinational Circuits
Multiplexers (MUX)
A MUX selects one input from many based on select lines. Also known as a Data Selector.
Decoders
Convert binary to specific line activations. Critical for RAM addressing and 7-Segment Displays.
- Address Decoding
- Instruction Decoding
- BCD to 7-Segment
Arithmetic Logic Unit (ALU)
The core of any processor. It combines adder circuits, muxes, and logic gates to perform arithmetic (Add, Sub) and logical (AND, OR, Shift) operations.
06. Sequential & State Machines
Master-Slave Logic
Solves timing hazards like the “Race Around Condition” by separating the sensing and output phase of a clock cycle.
3-Bit Binary Counter State Diagram
Sync Counters
All FF clocked together. High speed, no ripple delay.
Async Counters
Ripple effect clocks. Simple hardware but slower due to accumulated delay.
Mealy Machine
Output depends on both Present State and Present Inputs. Generally uses fewer states than Moore.
Moore Machine
Output depends only on the Present State. Inherently safer against input glitches.